Advantest Announces Memory Test System T5811 |
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Advantest Announces Memory Test System T5811 |
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| Focus on Memory Core Test Dramatically Lowers COT | |
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| Memory Test System T5811 | |
A New Solution for Commodity DRAM Test Cost Reduction |
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| Dynamic random access memory (DRAM) is the most commonly used type of commodity memory device for servers and client PCs, and is also used extensively in mobile applications. Solid bit growth in DDR3-SDRAM and DDR4-SDRAM, the dominant types of PC memory, augurs continuing market expansion. Meanwhile, the low-power requirements of smartphones and tablets underpin forecasts of rapidly growing demand for LPDDR2-SDRAM and LPDDR3-SDRAM. Yet the ongoing commodification of DRAM is driving down prices and forcing chipmakers to seek greater COT (cost of test) savings on their volume production lines. Backend DRAM test is commonly subdivided into memory core test and at-speed test. Advantest’s new T5811 memory test system offers a dramatic contribution to lower COT by focusing on core test. |
Product Features |
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| ETH Technology Dramatically Reduces COT |
| Advantest’s Enhanced Test Head (ETH) technology, a proprietary BOST configuration, holds down the cost of the tester mainframe by locating virtually all tester functionality on the motherboard in close proximity to the DUTs. ETH technology also enables upgradability via a simple switch-out of the Enhanced Test Module (ETM) component, allowing users to add functionality and improve test speed at will—contributing to significant COT reduction in the future as well as in the present. |
| 90% Lower Power Consumption, 2/3rds Smaller Footprint |
| The T5811 lowers power consumption by 90% and floor-space requirements by two-thirds, compared to previous testers, by utilizing Advantest’s proprietary ETH technology to locate virtually all tester functionality on the motherboard. |
| Simple Test Program Creation |
| The T5811 runs Advantest’s “Future Suite” tester OS, allowing operators to utilize the extensive library of program data created for T5xxx series test systems, regardless of whether BOST configuration is utilized. |
| Key Specifications |
| Target devices | : | LPDDR2/3-SDRAM, DDR3-SDRAM and DDR4-SDRAM cores | |
| Parallel test capacity | : | 512 (x8 I/O) | |
| Maximum test speed | : | 600MHz / 1.2Gbps | |
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| Strategic Business Unit, Global Marketing tel: +81-276-70-3300 |
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| Note: | All information supplied in this release is correct at the time of publication, but may be subject to change. |